Créer une présentation
Télécharger la présentation

Télécharger la présentation
## Mask Documentation of the EE/MatE129 Process Wafers

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -

**Mask Documentation of the EE/MatE129 Process Wafers**D. W. Parent SJSU**Overview**• The 4 mask NMOS process mask has many test structures: • Materials (Sheet resistance, Junction depth) • Diodes • MOS Capacitors (Long channel VT, Qss, NSUB • MOSFETS (KN, VT, g, l) • Circuits (Inverters, Current Mirrors, and Ring oscillators.)**Overview Continued**• These test structures provide data that the circuit design engineer uses to select W and L of a transistor to meet some circuit specification.**Materials**• These structures are used to measure • Sheet resistance of the aluminum or n-diffusion • Contact resistance between the aluminum and n diffusion • Mask registration Errors • Oxide Thickness • Junction depth**Diodes**• There are diode structures that can be used to measure • Junction capacitance • Side wall capacitance • Breakdown voltage • Io • Ideality factor (this is actually very hard)**MOS Capacitors**• MOS Caps are used to measure • Qss • Substrate doping • Sodium contamination**MOSFETS**• These are used to measure • KN, VT, g, l • Effective channel length and width**Circuits**• The inverter is used to measure: • Gain, Vinth, noise margins • The current mirror is used to measure how well transistors on the same wafer match each other. • The ring oscillator is used to measure • The ultimate speed of the MOSFETs • How many circuits can be integrated without a device failure.**Mask Overview**• Four Layers: • NDIFF • ACTIVE • CC • METAL1**Process Monitor Windows**Mask Overview Alignment Marks Alignment Marks Line Width Features**Alignment Marks**Use for 129**Mask Overview**Each test pattern is repeated in rows(Numbers) and columns (Letters) .**Verniers**Materials Field Oxide MOSFETS Cell Overview Diffused Resistors MOSCAPS Regular MOS Constant # Contact MOS Analog Leaf Cells Ring Oscillators Inverters**Cell Overview**Sheet Resistance Structures Diodes Metal Serpentines Inductors**-x**+x +y -y**Find the two Bars that line up perfectly.**Count how many bars from the center to the perfectly aligned bar. Multiply this by .5mm. This is your registration error. In this case the error is zero (plus or minus .5mm)**In this case the bar most perfectly aligned is this one.**Error in X=-3*.5mm=-1.5mm 3 2 1**Materials**Substrate-M1 Contact R NDIFF-M1 Contact R NDIFF RS M1 RS SUBSTRATE RS**Contact Resistance 1C**B A Force a current through A and D. Measure the voltage difference from B to C. D C l=5x10-4cm This will vary across chip. This is the as drawn length of the contact.**Contact Resistance 4C**Force a current through A and D. Measure the voltage difference from B to C. B A D C l=20x10-4cm This will vary across chip. This is the as drawn length of the contact.**NDIFF RS**A B Force a current through A and D. Measure the voltage difference from B to C. For a more accurate value you can Rotate the measurement and average the two RS values. D C**Metal1 RS**A B Force a current through A and D. Measure the voltage difference from B to C. For a more accurate value you can Rotate the measurement and average the two RS values. D C**Can be used to measure Sidewall**Junction Capacitance. Diodes Sweep a voltage across P to N and measure Current. Can be used to measure Bottom Junction Capacitance.**MOS Capacitors**Field Oxide Measure TOC with nanospec here. Use the MTI CV meter to extract VT, NSS, and NSUB. Use the TOX measured next to the MOSCAP. The as drawn diameter is 1000mm. YOu might have to stcrath Measure TOC with nanospec here. Gate Oxide**Regular MOSFETS**The width and the length change from 5x5mm up to 80x80mm.**Finding VT for a MOSFET**• Set VDS to less than the Vbi of the Drain/Body Junction (.2-.5V) • Sweep VGS from below VT to around 4-5 volts • If you are unsure of what VT is you can start at –5Volts • Measure ID • Plot gm(DID/DVG) vs. VGS • Find the xvalue for the maximum gm • Find the tangent the of ID-VGS at the value point • VT is where the line formed by the tangent intersects the x-axis.**ID**Tangent of ID at the xvalue that give gm-max gm-max gm ID VT**VT Numerical**IDmax=The ID at the point of maximum gm VGmax=The gate voltage at the point of maximum gm gmmax=The largest value of DID/DVG**KN**• Since Mobility varies with the electric field from Gate to body and source to drain KN=mnCox varies as well. This means KN is not a constant. One could take the average of the gm plot or use: This requires extensive testing and a regression. One could also report just gm-max.**Do a ID, BGS plot for different VSB voltages.**Body Effect (g)**Sample Regular MOSFET**The Body, Gate Source and Drain are already labeled. The bottom number is the as drawn length of the gate in microns. The top number is the as drawn width of the gate in microns.**Effective Channel Length**Measure ID VGS for several Gate Lengths.**Effective Channel Length**Calculate gm, and record gm max for each channel length.**Effective Channel Length**Plot 1/gm-max vs. as drawn channel length. Extrapolate this line until it cross the x-axis. Where this line crosses the x-axis is the DL of the process. Note since this is a simulation the line is perfectly straight. In measured devices you would have to do a regression. (This is easy to do in excel.) For this example DL is around .1um.**Constant Contact MOSFETs**These are used to try and extract spice level one models without varying the contact resistance, by keeping the same number of contacts.**Constant Drain/Source Resistance MOSFETS**These are used to try and extract spice level one models without varying the drain/source resistance.**Field Oxide MOSFETs**These MOSFETS use the field oxide for the gate oxide. Since the Filed oxide is much thicker that the active oxide layer, the VT should be much higher. However since we have a SOG layer over the field oxide, which has a Qss, the VT might be Negative! The mn x Cox will be much smaller in either case.**Inverter**Hold VDD constant (EE/MateE129~12Vs and sweep A from 0 to VDD. Measure Y**Plot the DVY/DVA.**Where the DVY/DVA curve equals –1 are the VIH and VIL points. In this case VIH=1V and VIL=2.9V. If there curve does not have two –1 cross points then it is not an inverter, and the ring oscillator will not work. Inverter**Inverter**VIH=1V VIL=2.9V**Average Propagation Delay**You need an oscilloscope and a power supply to measure this. Set the power supply voltage to the VDD value from the inverter test case. Measure the period of the waveform. T N=17, for EE129. In this case the average propagation delay is around 5ns.**Analog Leaf Cell**You hand stitch a current mirror circuit with Metal 1.**Current Mirror**Sweep VIN and Step IIN. One can see the channel narrowing affect causing errors between IIN and IOUT.